1. Field of the Invention
The present invention relates to an improvement to data processing systems employing volatile memory systems that utilize counters to access and refresh the storage devices. More particularly, it relates to a counter for use in a memory system wherein the parity of each count is determined and available for through-checking, and detects errors in counter operation as they occur.
2. State of the Prior Art
The use of binary counters in digital data processing systems has long been known. Counters have been employed in a variety of computing functions. An early and well-known use of a binary counter was to generate sequential addresses comprised of binary digits (bits) for accessing a memory for reading out stored instruction words sequentially for a binary digital data processing system. It was recognized at an early stage that errors in operation of such instruction address counters would cause the computing system to execute the incorrect sequence of instructions. Early attempts at checking for such counter errors involved the use of duplicate counters and the comparison of the results. A much improved system utilizing substantially fewer components involved the addition of logic circuits to the counter circuit that would generate the appropriate parity for successive counts. As is known, parity systems involve the use of additional bit positions to a group of bits for which parity is to be checked, wherein the additional bit position is assigned a value dependent upon the count of the one signals in the word. When odd parity is utilized, the parity bit will be set to a value one when the count of ones in the associated word is even. Alternatively, when the count of ones in the word is odd, the parity bit would be set to zero. The reverse conditions are employed when even parity is the system selected.
Determination of parity for a binary counter requires complex manipulation of each stage in the counter due to the fact that different numbers of bit positions will be altered for successive counts. A system that accomplishes parity generation for an instruction counter is shown in U.S. Pat. No. 3,192,362 to Cheney. A disadvantage of the system described by Cheney is the necessity of storing the current count and the next subsequent count so that parity can be evaluated and the actual count signal combinations can be compared.
In volatile memory systems, often referred to as dynamic memory systems, that utilize charge storage memory elements of the type requiring periodic refreshing to restore the contents thereof, a great deal of prior art exists surrounding the determination of appropriate systems to accomplish the refreshing functions. The memory array is typically comprised of a plurality of individual cells, arranged in rows and columns, whose binary representations are dependent on and determined by the capacitive charge that is stored therein. It is of course known, that if the volatile memory cells are not periodically refreshed either by direct addressing access, or by specific refreshing, the contents of the memory cells will be lost. Examples of this type of volatile memory cell include systems for storing a charge between the substrate and the gates of fieldeffect transistors, the storage of charge on capacitors having one or more associated transistors, or in some other charge storage structure. Example volatile memory devices are shown and described in U.S. Pat. No. 4,207,618 to White et al, and U.S. Pat. No. 3,387,286 to Dennard. The various types of memory cells will have different refresh timing requirements, it being understood that it is necessary to complete a refresh operation at least once during the device's Refresh Requirement Interval (RRI).
It is generally known that accessing memory cells for reading or writing does not occur simultaneously with accessing for refresh. In this regard, refreshing of memory cells is generally considered to be overhead to the operation of the system, with significant attempts made to minimize the impact of refresh on system operation.
One system of refresh can be considered to be the so-called "burst mode" of refresh. In systems of this type, care is taken to determine when it is necessary to refresh all or some major segment of the memory system, and when refresh is required, all accessing for reading and writing is interrupted temporarily. During this interruption, the memory is refreshed under control of a refresh counter. An example of this type of burst mode refreshing is shown in U.S. Pat. No. 3,387,286 to Dennard.
Another approach to refreshing the memory system has been designated the interleaved mode. In such systems, the control circuitry determines times of operation of when the access to the memory system will be neither reading nor writing. During such determined times, the system is free to refresh memory cells. The reading and writing is not interrupted per se, but is interleaved for access with refreshing on a noninterfering basis. An example of interleaved refreshing is shown and illustrated in U.S. Pat. 3,811,117 to Anderson et al. It is of course understood that interleaving of refresh may or may not provide sufficient access to the memory system to satisfy the Refresh Requirement Interval for all memory cells. In the event that it is not sufficient, the reading and writing functions may have to be interrupted to complete the refresh of the entire memory system within its RRI. Other examples of various refresh systems are shown in U.S. Pat. Nos. 4,357,686 to Scheuneman, 3,760,379 to Nibby et al., 3,719,932 to Cappon, 4,158,883 to Kadono et al., 4,084,154 to Panigrahi, 4,249,247 to Patel, and 3,810,129 to Behman et al.
In order to provide reliability of operation of data processing systems, there has been an ever-increasing use of through-checking techniques. "Through-checking" in this sense is understood to mean checking of data words or bit groupings through the use of parity or error correction code systems. The checking of transfers of data words or other bit groupings is often accomplished at major transfer points. For example, it is common in memory systems to utilize an error correction code system that allows memory to be checked for errors when data words are read out. Further, individual words or bit groupings are often checked at transfer points within the system. For example, a memory address is characteristically subjected to a parity check when transferred from the processing unit to the memory unit prior to accessing the memory. The concept of through-checking is being ever-expanded such that more and more transfer points are checked.
In the attempt to provide more reliable operations, system designers have also developed many techniques for circuitry to be self-checking to determine whether it is operating properly. Through the use of error detecting techniques and circuits, malfunctions can be detected, isolated, and identified for appropriate maintenance.
Prior art refresh systems have employed refresh counters, but have not provided through-checking capabilities in conjunction with error detecting capabilities.
Some dynamic memory systems employ a regenerate system. Memory addresses are periodically read out and the read data subjected to error detection and correction processes. When correctable errors are detected, the corrected data words are written back into the memory, thereby enhancing the probability of correct read out when accessed. As with the refresh system, a regenerate system must provide access control to all memory cells, but need not be in binary order.